January 2022 Archives by date
Starting: Tue Jan 4 02:44:46 UTC 2022
Ending: Sat Jan 29 12:13:27 UTC 2022
Messages: 155
- [riscv-port] RFR: 8279346: riscv: Unnecessary sign extension in BigInteger intrinsics
Fei Yang
- [riscv-port] Integrated: 8279346: riscv: Unnecessary sign extension in BigInteger intrinsics
Yanhong Zhu
- [riscv-port] RFR: 8278994: riscv: RVC support [v4]
Xiaolin Zheng
- [riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation instructions [v6]
Feilong Jiang
- [riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation instructions [v5]
Feilong Jiang
- [riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation instructions [v7]
Feilong Jiang
- [riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation instructions [v8]
Feilong Jiang
- [riscv-port] RFR: 8278994: riscv: RVC support [v5]
Xiaolin Zheng
- [riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation instructions [v8]
Fei Yang
- [riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation instructions [v9]
Feilong Jiang
- [riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation instructions [v9]
Fei Yang
- git: openjdk/riscv-port: riscv-port: 8 new changesets
duke
- Result: New RISC-V Port Committer: Yanhong Zhu
Yangfei (Felix)
- [riscv-port] RFR: 8279487: riscv: Fix bad AD file when UseRVB is disabled
Feilong Jiang
- [riscv-port] RFR: 8278994: riscv: RVC support [v5]
Yadong Wang
- [riscv-port] RFR: 8279487: riscv: Fix bad AD file when UseRVB is disabled
Fei Yang
- [riscv-port] RFR: 8279487: riscv: Fix bad AD file when UseRVB is disabled
Feilong Jiang
- [riscv-port] Integrated: 8279487: riscv: Fix bad AD file when UseRVB is disabled
Feilong Jiang
- [riscv-port] RFR: 8278994: riscv: RVC support [v6]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v5]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v7]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v5]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v8]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v8]
Fei Yang
- [riscv-port] RFR: 8278994: riscv: RVC support [v8]
Fei Yang
- [riscv-port] RFR: 8278994: riscv: RVC support [v9]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v8]
Xiaolin Zheng
- [riscv-port] RFR: 8279565: riscv: RVB: Add byte reverse instruction
Feilong Jiang
- [riscv-port] RFR: 8279565: riscv: RVB: Add byte reverse instruction [v2]
Feilong Jiang
- git: openjdk/riscv-port: riscv-port: 36 new changesets
duke
- [riscv-port] RFR: 8279565: riscv: RVB: Add byte reverse instruction [v3]
Feilong Jiang
- [riscv-port] RFR: 8279565: riscv: RVB: Add byte reverse instruction [v3]
Feilong Jiang
- [riscv-port] RFR: 8279565: riscv: RVB: Add byte reverse instruction [v3]
Fei Yang
- [riscv-port] RFR: 8279565: riscv: RVB: Add byte reverse instruction [v3]
Feilong Jiang
- [riscv-port] Integrated: 8279565: riscv: RVB: Add byte reverse instruction
Feilong Jiang
- [riscv-port] RFR: 8278994: riscv: RVC support [v10]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v10]
Fei Yang
- [riscv-port] RFR: 8278994: riscv: RVC support [v10]
Fei Yang
- [riscv-port] RFR: 8278994: riscv: RVC support [v11]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v10]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v10]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v10]
Fei Yang
- [riscv-port] RFR: 8278994: riscv: RVC support [v12]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v10]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v10]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v10]
Fei Yang
- [riscv-port] RFR: 8278994: riscv: RVC support [v10]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v13]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v10]
Fei Yang
- git: openjdk/riscv-port: riscv-port: 7 new changesets
duke
- [riscv-port] RFR: 8278994: riscv: RVC support [v14]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v10]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v14]
Fei Yang
- git: openjdk/riscv-port: riscv-port: 28 new changesets
duke
- [riscv-port] RFR: 8279827: riscv: RVB: Add shift and add instructions
Feilong Jiang
- [riscv-port] RFR: 8279827: riscv: RVB: Add shift and add instructions [v2]
Feilong Jiang
- [riscv-port] RFR: 8279827: riscv: RVB: Add shift and add instructions [v2]
Yanhong Zhu
- [riscv-port] RFR: 8279827: riscv: RVB: Add shift and add instructions [v2]
Fei Yang
- [riscv-port] RFR: 8279827: riscv: RVB: Add shift and add instructions [v3]
Feilong Jiang
- [riscv-port] RFR: 8279827: riscv: RVB: Add shift and add instructions [v4]
Feilong Jiang
- [riscv-port] RFR: 8279827: riscv: RVB: Add shift and add instructions [v4]
Feilong Jiang
- [riscv-port] RFR: 8279827: riscv: RVB: Add shift and add instructions [v2]
Feilong Jiang
- [riscv-port] RFR: 8278994: riscv: RVC support [v14]
Xiaolin Zheng
- [riscv-port] RFR: 8279827: riscv: RVB: Add shift and add instructions [v4]
Fei Yang
- [riscv-port] RFR: 8279827: riscv: RVB: Add shift and add instructions [v4]
Feilong Jiang
- [riscv-port] RFR: 8279827: riscv: RVB: Add shift and add instructions [v4]
Yanhong Zhu
- [riscv-port] Integrated: 8279827: riscv: RVB: Add shift and add instructions
Feilong Jiang
- [riscv-port] RFR: 8278994: riscv: RVC support [v14]
Fei Yang
- [riscv-port] RFR: 8278994: riscv: RVC support [v15]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v14]
Xiaolin Zheng
- [riscv-port] RFR: 8279914: riscv:Wrong result caused by incorrect use of iregL2I operand in some c2 match rules
Feilong Jiang
- [riscv-port] RFR: 8279914: riscv:Wrong result caused by incorrect use of iregL2I operand in some c2 match rules [v2]
Feilong Jiang
- [riscv-port] RFR: 8279914: riscv: Wrong result caused by incorrect use of iregL2I operand in some c2 match rules [v3]
Feilong Jiang
- [riscv-port] RFR: 8279914: riscv: Wrong result caused by incorrect use of iregL2I operand in some c2 match rules [v3]
Fei Yang
- [riscv-port] Integrated: 8279914: riscv: Wrong result caused by incorrect use of iregL2I operand in some c2 match rules
Feilong Jiang
- git: openjdk/riscv-port: riscv-port: 41 new changesets
duke
- [riscv-port] RFR: 8278994: riscv: RVC support [v16]
Xiaolin Zheng
- [riscv-port] RFR: 8279996: riscv: RVB: Add zeros/population count instructions
Feilong Jiang
- [riscv-port] RFR: 8279996: riscv: RVB: Add zeros/population count instructions
Fei Yang
- [riscv-port] RFR: 8279996: riscv: RVB: Add zeros/population count instructions [v2]
Feilong Jiang
- [riscv-port] RFR: 8279996: riscv: RVB: Add zeros/population count instructions [v2]
Fei Yang
- [riscv-port] Integrated: 8279996: riscv: RVB: Add zeros/population count instructions
Feilong Jiang
- [riscv-port] RFR: 8278994: riscv: RVC support [v16]
Yadong Wang
- [riscv-port] RFR: 8279826: riscv: Preserve result in native wrapper with +UseHeavyMonitors
Yadong Wang
- [riscv-port] RFR: 8279826: riscv: Preserve result in native wrapper with +UseHeavyMonitors
Feilong Jiang
- [riscv-port] RFR: 8278994: riscv: RVC support [v16]
Yadong Wang
- [riscv-port] RFR: 8278994: riscv: RVC support [v17]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v16]
Xiaolin Zheng
- [riscv-port] RFR: 8279826: riscv: Preserve result in native wrapper with +UseHeavyMonitors
Fei Yang
- [riscv-port] Integrated: 8279826: riscv: Preserve result in native wrapper with +UseHeavyMonitors
Yadong Wang
- git: openjdk/riscv-port: riscv-port: 29 new changesets
duke
- [riscv-port] RFR: 8278994: riscv: RVC support [v18]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v18]
Fei Yang
- [riscv-port] RFR: 8278994: riscv: RVC support [v19]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v18]
Xiaolin Zheng
- [riscv-port] RFR: 8278994: riscv: RVC support [v19]
Fei Yang
- [riscv-port] RFR: 8278994: riscv: RVC support [v19]
Xiaolin Zheng
- [riscv-port] Integrated: 8278994: riscv: RVC support
Xiaolin Zheng
- [riscv-port] RFR: 8280116: riscv: RVB: Add rest instructions of zba, zbb, and bitwise rotation
Feilong Jiang
- [riscv-port] RFR: 8280116: riscv: RVB: Add rest instructions of zba, zbb, and bitwise rotation
Fei Yang
- git: openjdk/riscv-port: riscv-port: 25 new changesets
duke
- [riscv-port] RFR: 8280116: riscv: RVB: Add rest instructions of zba, zbb, and bitwise rotation [v2]
Feilong Jiang
- [riscv-port] RFR: 8280116: riscv: RVB: Add rest instructions of zba, zbb, and bitwise rotation [v2]
Feilong Jiang
- [riscv-port] Integrated: 8280116: riscv: RVB: Add rest instructions of zba, zbb, and bitwise rotation
Feilong Jiang
- git: openjdk/riscv-port: riscv-port: 21 new changesets
duke
- [riscv-port] RFR: 8280236: riscv: Minimal build failed after JDK-8279565
Feilong Jiang
- [riscv-port] RFR: 8280236: riscv: Minimal build failed after JDK-8279565
Fei Yang
- [riscv-port] Integrated: 8280236: riscv: Minimal build failed after JDK-8279565
Feilong Jiang
- git: openjdk/riscv-port: riscv-port: 61 new changesets
duke
- [riscv-port] RFR: 8279664: riscv: JFR crashes at 0x0
Xiaolin Zheng
- [riscv-port] RFR: 8279664: riscv: JFR crashes at 0x0
Yadong Wang
- git: openjdk/riscv-port: riscv-port: 16 new changesets
duke
- [riscv-port] RFR: 8279664: riscv: JFR crashes at 0x0
Fei Yang
- [riscv-port] RFR: 8279664: riscv: JFR crashes at 0x0 [v2]
Xiaolin Zheng
- [riscv-port] RFR: 8279664: riscv: JFR crashes at 0x0 [v2]
Xiaolin Zheng
- [riscv-port] RFR: 8279664: riscv: JFR crashes at 0x0 [v2]
Fei Yang
- [riscv-port] RFR: 8279664: riscv: JFR crashes at 0x0 [v3]
Xiaolin Zheng
- [riscv-port] RFR: 8279664: riscv: JFR crashes at 0x0 [v3]
Xiaolin Zheng
- [riscv-port] RFR: 8279664: riscv: JFR crashes at 0x0 [v3]
Fei Yang
- [riscv-port] RFR: 8279664: riscv: JFR crashes at 0x0 [v3]
Xiaolin Zheng
- [riscv-port] Integrated: 8279664: riscv: JFR crashes at 0x0
Xiaolin Zheng
- [riscv-port] RFR: 8280423: riscv: Unnecessary i2l conversion in LIRGenerator::emit_array_address
Feilong Jiang
- [riscv-port] RFR: 8280423: riscv: Unnecessary i2l conversion in LIRGenerator::emit_array_address
Feilong Jiang
- [riscv-port] Withdrawn: 8280423: riscv: Unnecessary i2l conversion in LIRGenerator::emit_array_address
Feilong Jiang
- [riscv-port] RFR: 8280423: riscv: Unnecessary i2l conversion in LIRGenerator::emit_array_address
Feilong Jiang
- [riscv-port] RFR: 8280423: riscv: Unnecessary i2l conversion in LIRGenerator::emit_array_address
Fei Yang
- [riscv-port] RFR: 8280423: riscv: Unnecessary i2l conversion in LIRGenerator::emit_array_address
Yanhong Zhu
- [riscv-port] RFR: 8280423: riscv: Unnecessary i2l conversion in LIRGenerator::emit_array_address
Feilong Jiang
- [riscv-port] Integrated: 8280423: riscv: Unnecessary i2l conversion in LIRGenerator::emit_array_address
Feilong Jiang
- [riscv-port] RFR: 8280424: riscv: fix saved_fp for compiled frame in frame::safe_for_sender
Yanhong Zhu
- [riscv-port] RFR: 8280424: riscv: fix saved_fp for compiled frame in frame::safe_for_sender
Fei Yang
- [riscv-port] Integrated: 8280424: riscv: fix saved_fp for compiled frame in frame::safe_for_sender
Yanhong Zhu
- git: openjdk/riscv-port: riscv-port: 9 new changesets
duke
- git: openjdk/riscv-port: riscv-port: 28 new changesets
duke
- git: openjdk/riscv-port: riscv-port: 20 new changesets
duke
- [riscv-port] RFR: 8280497: riscv: Undefined Behaviour in class Assembler
Yadong Wang
- [riscv-port] RFR: 8280497: riscv: Undefined Behaviour in class Assembler
Fei Yang
- [riscv-port] RFR: 8280497: riscv: Undefined Behaviour in class Assembler [v2]
Yadong Wang
- [riscv-port] RFR: 8280497: riscv: Undefined Behaviour in class Assembler [v2]
Fei Yang
- [riscv-port] RFR: 8280497: riscv: Undefined Behaviour in class Assembler [v2]
Feilong Jiang
- git: openjdk/riscv-port: riscv-port: 19 new changesets
duke
- [riscv-port] Integrated: 8280497: riscv: Undefined Behaviour in class Assembler
Yadong Wang
- [riscv-port] RFR: 8278847: riscv: Intrinsify BigInteger.montgomeryMultiply
Yanhong Zhu
- [riscv-port] RFR: 8278847: riscv: Intrinsify BigInteger.montgomeryMultiply
Fei Yang
- [riscv-port] Integrated: 8278847: riscv: Intrinsify BigInteger.montgomeryMultiply
Yanhong Zhu
- [riscv-port] RFR: 8280683: riscv: Remove uses of long and unsigned long
Yadong Wang
- [riscv-port] RFR: 8280683: riscv: Remove uses of long and unsigned long
Fei Yang
- [riscv-port] RFR: 8280683: riscv: Remove uses of long and unsigned long [v2]
Yadong Wang
- [riscv-port] RFR: 8280683: riscv: Remove uses of long and unsigned long [v2]
Fei Yang
- [riscv-port] Integrated: 8280683: riscv: Remove uses of long and unsigned long
Yadong Wang
- [riscv-port] RFR: 8280845: riscv: Intrinsify BigInteger.montgomerySquare
Yanhong Zhu
- git: openjdk/riscv-port: riscv-port: 20 new changesets
duke
- [riscv-port] RFR: 8280845: riscv: Intrinsify BigInteger.montgomerySquare
Fei Yang
- [riscv-port] Integrated: 8280845: riscv: Intrinsify BigInteger.montgomerySquare
Yanhong Zhu
- git: openjdk/riscv-port: riscv-port: 10 new changesets
duke
Last message date:
Sat Jan 29 12:13:27 UTC 2022
Archived on: Sat Jan 29 12:13:33 UTC 2022
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