[riscv-port] RFR: 8278994: riscv: RVC support [v5]
Yadong Wang
yadongwang at openjdk.java.net
Wed Jan 5 03:50:51 UTC 2022
On Tue, 4 Jan 2022 04:34:11 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:
>> Hi team,
>>
>> This patch includes the basic definition of the RVC instruction set and some cleanups. Tested a simple `test/hotspot/jtreg/compiler/` folder on qemu.
>>
>> Using `<JAVA_HOME>/bin/java -XX:+UnlockExperimentalVMOptions -XX:+UseRVC -XX:+UnlockDiagnosticVMOptions -XX:+PrintAssembly -XX:PrintAssemblyOptions=no-aliases,numeric -XX:+PrintStubCode -XX:-TieredCompilation` could show RVC instructions.
>>
>> Thanks,
>> Xiaolin
>
> Xiaolin Zheng has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR.
src/hotspot/cpu/riscv/assembler_riscv.hpp line 431:
> 429: INSN(remu, 0b0110011, 0b111, 0b0000001, NOT_COMPRESSIBLE);
> 430: INSN(remw, 0b0111011, 0b110, 0b0000001, NOT_COMPRESSIBLE);
> 431: INSN(remuw, 0b0111011, 0b111, 0b0000001, NOT_COMPRESSIBLE);
Shall we arrange the instructions to 2 groups (compressible and non-compressible), instead of crossing each other?
src/hotspot/cpu/riscv/c2_globals_riscv.hpp line 49:
> 47: define_pd_global(intx, FreqInlineSize, 325);
> 48: define_pd_global(intx, MinJumpTableSize, 10);
> 49: define_pd_global(intx, InteriorEntryAlignment, 4);
It's best to keep InteriorEntryAlignment and CodeEntryAlignment unchanged if there's no obvious benefits.
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PR: https://git.openjdk.java.net/riscv-port/pull/34
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