[riscv-port] RFR: 8278994: riscv: RVC support [v10]

Fei Yang fyang at openjdk.java.net
Sat Jan 8 11:18:04 UTC 2022


On Fri, 7 Jan 2022 08:36:47 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> Hi team,
>> 
>> This patch includes the basic definition of the RVC instruction set and some cleanups. Tested a simple `test/hotspot/jtreg/compiler/` folder on qemu.
>> 
>> Using `<JAVA_HOME>/bin/java -XX:+UnlockExperimentalVMOptions -XX:+UseRVC -XX:+UnlockDiagnosticVMOptions -XX:+PrintAssembly -XX:PrintAssemblyOptions=no-aliases,numeric -XX:+PrintStubCode -XX:-TieredCompilation` could show RVC instructions.
>> 
>> Thanks,
>> Xiaolin
>
> Xiaolin Zheng has updated the pull request with a new target base due to a merge or a rebase. The pull request now contains 14 commits:
> 
>  - Move RVC code to the proper location after rebasing (#42)
>  - Rename misc functions and change the positions of some comments
>  - Remove remaining macros as discussions
>  - Remain an 'minimum_alignment' unchanged
>  - Manually inline all macros into functions as discussions
>  - Remove assembler_riscv_c.hpp as discussions
>  - Remove COMPRESSIBLE & NOT_COMPRESSIBLE macros by adding one layer as discussions
>  - Fix remaining CEXT -> RVC
>  - Remove Alignment-related changes as discussions
>  - Update licenses to the new year
>  - ... and 4 more: https://git.openjdk.java.net/riscv-port/compare/c7944edf...2a6ff151

src/hotspot/cpu/riscv/assembler_riscv.hpp line 2053:

> 2051: 
> 2052:   // RVC: extract a 16-bit instruction.
> 2053:   static inline uint16_t c_extract(uint16_t val, unsigned msb, unsigned lsb) {

Looks like c_extract and c_sextract are not used?

src/hotspot/cpu/riscv/assembler_riscv.hpp line 2409:

> 2407:   }
> 2408: 
> 2409: #define IF(BOOL, ...)       IF_##BOOL(__VA_ARGS__)

maybe better to expand those macros directly?

src/hotspot/cpu/riscv/riscv.ad line 1194:

> 1192: 
> 1193: // RVC: With RVC a call may get 2-byte aligned.
> 1194: //   The offset encoding in jal ranges bits [12, 31], which could span the cache line.

Maybe rephrasing like this:
//   The offset encoding in jal ranges bits [12, 31] could span the cache line.

src/hotspot/cpu/riscv/riscv.ad line 1204:

> 1202: }
> 1203: 
> 1204: // RVC: With RVC a call may get 2-byte aligned.

Looks like this comment dupliates the one for CallStaticJavaDirectNode::compute_padding.

src/hotspot/cpu/riscv/vm_version_riscv.cpp line 109:

> 107:   }
> 108: 
> 109:   // compressed instruction extension

I think this should better to place this one after UseRVV and UseRVB.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/34


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