[riscv-port] RFR: 8279827: riscv: RVB: Add shift and add instructions [v4]
Fei Yang
fyang at openjdk.java.net
Wed Jan 12 06:21:01 UTC 2022
On Wed, 12 Jan 2022 01:44:21 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:
>> This PR implements shift left and add instructions: `sh1add`/`sh2add`/`sh3add`/`sh1add.uw`/`sh2add.uw`/`sh3add.uw`.
>>
>> New C2 instructions are covered by JTREG test: test/jdk/java/lang
>>
>> Hotspot and jdk tier1 tests on QEMU (with and without UseRVB) are passed without new failures.
>
> Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:
>
> fix build error
Looks good. Thanks.
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Marked as reviewed by fyang (Lead).
PR: https://git.openjdk.java.net/riscv-port/pull/43
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