Re: Discuss the RVC implementation

Xiaolin Zheng yunyao.zxl at
Tue Oct 11 05:20:22 UTC 2022

Hi team,
Following up on the performance data on SPECjbb2015 (composite mode) for RVC.
These days I have been going in for some performance data on SPECjbb2015.
Shortly, there seems to be a (maybe) 1.5%~2.5% performance gain of mutators under some observations and it might be reasonable for it aligns the results I have observed. Results are at [0].
Saying "maybe" because the SPECjbb2015 results on my Hifive Unmatched board seem to have a ~±5% fluctuations and I think they are reasonable too. So there's a question of if the seeming performance gain is legal or not.
Wrote a simple program to calculate the average max-JOPS results for convenience.
(There has been a result from philosophers evaluating the "whitelist mode" implementation of RVC, see [1]; I follow a similar style.)
Let us have 
[A] RVC branch at [2] but without the histogram patch
[B] The simple unaligned access patch at [3] for I am interested in the unaligned access thing (though reading from the results afterward it seems to behave normally, having nothing special)
1. [A] + [B] + g1 < >
Mutators seem to have a 1.69% gain; The T.TEST result, shows the confidence level is only 62%, with 2-tailed.
2. [A] + [B] + parallel gc < >
There seems to have a 2.62% gain; The T.TEST result shows the confidence level is 98.6%, so seems okay.
3. [A] + g1 < >
Seems a 3.64% gain? A confidence level 99.1% is shown by Excel; but I doubt it a bit because I have never observed such data though. The max-JOPS data at last are too high to be considered normal. I guess my board overdosed at that time, so I keep a reserved attitude toward it.
4. [A] + parallel gc < >
I just invoked this yesterday so the sample data is not enough. I didn't drop the lowest/highest results this time accordingly.
Showing a 1.5% gain, the confidence level is only 70% though. (maybe samples are not big enough)
Evaluated on a general Hifive Unmatched board which (seemingly) we all have, so the results should be reproducible I guess.
Though I believe there should be performance gain theoretically in generated code for the potential "I-cache enlargement" from RVC's code size reduction, well, for this feature currently I think no regression is enough though. The performance gain from RVC is a special bonus to me (or to us), so this post is just showing some evaluations to follow up on the performance aspect mentioned weeks ago.
Accordingly, going to submit a PR for the rest part of RVC (to implement the "blacklist mode").
[0] < >
[1] < >
[2] < >
[3] < >
From:yangfei <yangfei at>
Send Time:2022年9月17日(星期六) 21:12
To:郑孝林(云矅) <yunyao.zxl at>
Cc:riscv-port-dev <riscv-port-dev at>
Subject:Re: Discuss the RVC implementation
 Hi Xiaolin, 
 Your new proposal for supporting the RVC extension looks interesting. 
 May I ask if you have any performance data including code size measured? 
 Also it's appreciated if you have more details about the issue with MachBranch nodes. 
 -----Original Messages-----
From:"Xiaolin Zheng" <yunyao.zxl at>
Sent Time:2022-09-15 10:52:59 (Thursday)
To: riscv-port-dev <riscv-port-dev at>
Subject: Discuss the RVC implementation
 Hi team, 
 I am going to describe a different implementation of RVC for our backend. 
 ## Background
 The RISC-V C extension, also known as RVC, could transform 4-byte instructions to 2-byte counterparts when eligible (for example, as the manual, Rd/Rs of instruction ranges from [x8,x15] might be one common requirement, etc.).
 ## The current implementation in the Hotspot 
 The current implementation[0] is a transient one, introducing a "CompressibleRegion" by using RTTI[1] to indicate that instructions inside these regions can be safely substituted by the RVC counterparts, if convertible; and the implementation also uses a, say, "whitelist mode" by using the "CompressibleRegion" mentioned above to "manually mark out safe regions", then batch emit them if could. However, after a deeper look, we might discover the current "whitelist mode" has several shortages: 
 ## Shortages of the current implementation 
 1. Coverages: 
 The current implementation only covers some of C2 match rules, and only some small part of stub code, so there is obviously far more space to reduce the total code size. In my observations, some RISC-V instruction sequences generally occupy a bit more space than AArch64 ones[2]. With the new implementations, we could achieve a code size level alike AArch64's generated code. Some better, some still worse than AArch64 one in my simple observation. 
 2. Though safe, I'd say it's very much not easy to maintain. The background is, most of the patchable instructions cannot be easily transformed into their shorter counterparts[3], and they need to be prevented from being compressed. So comes the question: we must make sure no patchable relocation is inside the range of a "CompressibleRegion". For example, the string comparison intrinsic function[4] looks very delicious: transforming it and its siblings may result in a yummy compression rate. But programmers might have to check lots of its callees to find if there is just one patchable relocation hidden inside that causes the whole intrinsic incompressible. This could cause extra burden for programmers, so I bet no one would like to add "CompressibleRegion" for his/her code :-) 
 3. Performance: 
 Better performance of generated code is a little side effect this extension gives us, the smaller the I$ size, the better performance though - please see Andrew Waterman's paper[5] for more reference there. Anyway, it looks like a higher general compression rate is better for performance. 
 The main issue here is the granularity of "CompressibleRegion" is a bit coarse. "Why not exclude the incompressible parts" may come up to us naturally. And after some diggings, we may find: we just need to exclude countable places that would be patched back (mostly relocations), and several code slices with a fixed length, which will be calculated, such as "emit_static_call_stub". All remaining instructions could be safely transformed into RVC counterparts if eligible. So maybe, say, the "blacklist mode"? 
 ## The new implementation 
 To implement the "blacklist mode" in the backend, we need two things: 
 1. an "IncompressibleRegion", indicating instructions inside it should remain in their normal 4-byte form no matter what happens. 
 2. a simple strategy to exclude patchable instructions, mainly for relocations. So we can see the new strategy is highly bounded to relocations' positions: 
 We all know the "relocate()" in Hotspot VM is a mark that only has an explicit "start point" without an end point, and some of them could be patched back. Therefore, we can use a simple strategy: introduce a lambda as another argument to assign "end point" semantics to the relocations, for completing our requirements without extra costs. For example: 
 __ relocate(safepoint_pc.rspec()); 
 __ la(t0,; 
 __ sd(t0, Address(xthread, JavaThread::saved_exception_pc_offset())); 
 After introducing a simple lambda as an extra argument: 
 __ relocate(safepoint_pc.rspec(), [&] { // The relocate() hides an "IncompressibleRegion" in it 
 __ la(t0,; // This patchable instruction sequence is incompressible 
 _ sd(t0, Address(xthread, JavaThread::saved_exception_pc_offset())); 
 Well, simple but effective. Excluding such countable dynamically patchable places and unifying all relocations, all other instructions can be safely transformed, without messing up the current code style. Programmers could just keep aligning the same style; most of the time they have no need to care about whether the RVC exists or not and things get converted automatically. The proposed new sample code is again, here[6]. 
 ## Other things worth being noticed 
 1. Instruction patching issues
 With the C extension, the backend mixes with both 2-byte and 4-byte instructions. It gets a little CISC alike. We know the Hotspot would patch instructions when code is running at full speed, such as call instructions, nops used for deoptimizations (the nops at the entry points, and post-call nops after loom). Instruction patching is delicate so we must carefully handle such places, to keep these 4-byte instructions from spanning cachelines. Though remaining a 4-byte normal form even with RVC, they might sit at a 2-byte aligned boundary. Such cases should definitely not happen, for patching such places spanning cachelines would lose the atomicity. So shortly, we must properly align them, such as [7][8]. Such a problem could exist with RVC, no matter "whitelist mode" or "blacklist mode". It is a general problem for instruction patching. I will add more strong assertions to the potential places (trampoline_call might be a very good spot, for patchable "static_call", "opt_virtual" and "virtual" relocations) to check alignment in the future patches. 
 2. MachBranch Nodes 
 And MachBranch nodes: they are not easy to be tamed because the "fake label"[9] in PhaseOutput::scratch_emit_size() cannot tell us the real distance of the label. But we can leave them alone in this discussion, for there will be patches to handle those afterward. 
 That's nearly all. Thanks for reaching here despite the verbosity. It would be very nice to receive any suggestions. 
 [0] Original patch: < > 
 [1] Of course, the "CompressibleRegion" is good, I like it; and this idea is not from myself. 
 [2] For a simple example, a much commonly used fixed-length movptr() uses up six 4-byte instructions (lui+addi+slli+addi+slli+addi, MIPS alike instructions using arithmetical calculations with signed extensions, but not anyone's fault :-) ), while the AArch64 counterpart only takes three 4-byte instructions (movz+movk+movk). They are both going to mov a 48-bit immediate. After accumulation, the size differs quite a lot. 
 [3] 2-byte instructions have fewer bits, so comes shorter immediate encoding etc. compared to the 4-byte counterparts. After we transform patchable instructions (ones at marks of patchable relocations, etc.) to 2-byte ones, when they are patched to a larger value or farther distances afterward, it is possible that they sadly find themselves, the shorter instructions, cannot cover the newly patched value. So we need to exclude patchable instructions (at the relocation marks etc.) from being compressed. 
 [4] < > 
 [5] < >, Page 64: "5.4 The RVC Extension, Performance Implications" 
 [6] < > 
 [7] < > 
 [8] < > 
[9] < > 
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