[riscv-port-jdk17u:riscv-port] RFR: 8296447: RISC-V: Make the operands order of vrsub_vx/vrsub_vi consistent with RVV 1.0 spec

[Dingli Zhang]

Please review this backport to riscv-port-jdk17u.
Backport of [JDK-8296447](https://bugs.openjdk.org/browse/JDK-8296447). 
A little conflict is that we do not have the `vneg_v` in `macroAssembler_riscv.cpp`

Testing:
- jdk/incubator/vector (release/fastdebug with UseRVV on QEMU)

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Commit messages:
 - 8296447: RISC-V: Make the operands order of vrsub_vx/vrsub_vi consistent with RVV 1.0 spec

Changes: https://git.openjdk.org/riscv-port-jdk17u/pull/41/files
 Webrev: https://webrevs.openjdk.org/?repo=riscv-port-jdk17u&pr=41&range=00
  Issue: https://bugs.openjdk.org/browse/JDK-8296447
  Stats: 20 lines in 2 files changed: 1 ins; 11 del; 8 mod
  Patch: https://git.openjdk.org/riscv-port-jdk17u/pull/41.diff
  Fetch: git fetch https://git.openjdk.org/riscv-port-jdk17u.git pull/41/head:pull/41

PR: https://git.openjdk.org/riscv-port-jdk17u/pull/41