[riscv-port-jdk17u:riscv-port] RFR: 8297715: RISC-V: C2: Use single-bit instructions from the Zbs extension

[Fei Yang]

On Thu, 23 Mar 2023 16:17:36 GMT, Dingli Zhang <dzhang at openjdk.org> wrote:

> Please review this backport to riscv-port-jdk17u.
> Backport of [JDK-8297715](https://bugs.openjdk.org/browse/JDK-8297715).
> The original patch cannot be directly applied because of the line number, but there are no other additional changes.
> 
> The effect is that we could then optimize C2 JIT code for methods like (print with case `xml.validation` in SPECjvm2008):
> Before:
> 
> 03c     lhu  R28, [R11, #12]	# short, #@loadUS ! Field: com/sun/org/apache/xerces/internal/dom/NodeImpl.flags
> 040 +   andi  R7, R28, #2	#@andI_reg_imm
> 044 +   snez  R10, R7	#@convI2Bool
> 
> After:
> 
> 03c     lhu  R28, [R11, #12]	# short, #@loadUS ! Field: com/sun/org/apache/xerces/internal/dom/NodeImpl.flags
> 040 +   bexti  R10, R28, #2	#@convI2Bool_andI_reg_immIpowerOf2
> 
> 
> Testing:
> - Tier1 passed without new failure on qemu (release) using `-XX:+UnlockExperimentalVMOptions -XX:+UseZbs`.

Looks good.

-------------

Marked as reviewed by fyang (Committer).

PR Review: https://git.openjdk.org/riscv-port-jdk17u/pull/26#pullrequestreview-1358220859