[riscv-port-jdk17u:riscv-port] RFR: 8308277: RISC-V: Improve vectorization of Match.sqrt() on floats

[Feilong Jiang]

On Mon, 22 May 2023 10:40:45 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

> Hi,
> Please review this clean backport of [JDK-8308277](https://bugs.openjdk.org/browse/JDK-8308277).
> 
> For jdk17u, `Math.sqrt(float)` will not get vectorized even when `UseRVV` is true without the `SqrtF` node.
> 
> Here is the OptoAssembly of Sqrt.java from [JDK-8190800](https://bugs.openjdk.org/browse/JDK-8190800):
> 
> before:
> 
> 120     B14: #  out( B14 B15 ) <- in( B13 B14 ) Loop( B14-B14 inner main of N91 strip mined) Freq: 1.86254e+07
> 120 +   addw  R28, R12, zr  #@convI2L_reg_reg
> 124 +   slli  R28, R28, (#2 & 0x3f) #@lShiftL_reg_imm
> 128 +   add R28, R18, R28   # ptr, #@addP_reg_reg
> 12c +   flw  F0, [R28, #16] # float, #@loadF
> 130 +   fsqrt.s  F1, F0 #@sqrtF_reg
> 134 +   fsw  F1, [R28, #16] # float, #@storeF
> 
> 
> after:
> 
> 140     B14: #  out( B14 B15 ) <- in( B13 B14 ) Loop( B14-B14 inner main of N93 strip mined) Freq: 1.60517e+07
> 140     addw  R10, R31, zr  #@convI2L_reg_reg
> 144     slli  R10, R10, (#2 & 0x3f) #@lShiftL_reg_imm
> 148     add R11, R9, R10    # ptr, #@addP_reg_reg
> 14c     addi  R10, R11, #16 # ptr, #@addP_reg_imm
> 150     vle V1, [R10]   #@loadV
> 158     vfsqrt.v V1, V1 #@vsqrtF
> 160     addi  R10, R11, #16 # ptr, #@addP_reg_imm
> 164     vse V1, [R10]   #@storeV

tier1 looks good.

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PR Comment: https://git.openjdk.org/riscv-port-jdk17u/pull/58#issuecomment-1562117141