[riscv-port-jdk17u:riscv-port] Integrated: 8301852: RISC-V: Optimize class atomic when order is memory_order_relaxed

[Dingli Zhang]

On Wed, 24 May 2023 07:55:27 GMT, Dingli Zhang <dzhang at openjdk.org> wrote:

> Hi, please review this backport to riscv-port-jdk17u.
> Backport of [JDK-8301852](https://bugs.openjdk.org/browse/JDK-8301852). Applies cleanly.
> 
> Testing:
> - Tier1-3 passed without new failure on unmacthed (release).

This pull request has now been integrated.

Changeset: bac6ef76
Author:    Dingli Zhang <dzhang at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.org/riscv-port-jdk17u/commit/bac6ef76ced0e997f820a2ef8fa0c5c16cd28d07
Stats:     36 lines in 1 file changed: 18 ins; 1 del; 17 mod

8301852: RISC-V: Optimize class atomic when order is memory_order_relaxed

Reviewed-by: fyang
Backport-of: 1fec6b5953b51dae4be640d6e4e4f79136b9348d

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PR: https://git.openjdk.org/riscv-port-jdk17u/pull/60