RFR: 8252204: AArch64: Implement SHA3 accelerator/intrinsic [v11]

[Yudi Zheng]

On Wed, 2 Aug 2023 12:33:43 GMT, Ferenc Rakoczi <duke at openjdk.org> wrote:

>> src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp line 3473:
>> 
>>> 3471:     __ bcax(v24, __ T16B, v24, v8,  v31);
>>> 3472: 
>>> 3473:     __ ld1r(v31, __ T2D, __ post(rscratch1, 8));
>> 
>> is it intentional to load 16 bytes and post-increment by 8?
>
> Actually, with the ld1r instruction the post increment should be the same as the size of the memory accessed. So T2D requires 8 as it reads 8 bytes(and duplicates it into both halves of the SIMD register).

Thanks for the clarification!

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PR Review Comment: https://git.openjdk.org/jdk/pull/207#discussion_r1281961206