RFR: 8252857: AArch64: Shenandoah C1 CAS is not sequentially consistent

[Andrew Haley]

On 21/09/2020 10:11, Nick Gasson wrote:
> C1 atomic operations are supposed to be sequentially consistent by
> default but the variant in the Shenandoah C1 barrier set assembler only
> provides a half-barrier when the CAS succeeds. Added a trailing full
> barrier and load-acquire to exactly match the non-Shenandoah C1 CAS
> implementation. This prevents any memory accesses following the CAS
> operation being observed before it.

We only need the trailing membar if is_c1_or_interpreter_only(). Otherwise
all volatile loads in C1 are preceded by a leading membar() so we don't
need a trailing one as well.

>> 462 // By default, this operation has relaxed memory ordering

No, it has whatever memory ordering you tell it. Plus, if you pass
both acquire and release, sequential consistency.

-- 
Andrew Haley  (he/him)
Java Platform Lead Engineer
Red Hat UK Ltd. <https://www.redhat.com>
https://keybase.io/andrewhaley
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