RFR: 8252857: AArch64: Shenandoah C1 CAS is not sequentially consistent

[Nick Gasson]

On 09/21/20 18:23 pm, Andrew Haley wrote:
>
> We only need the trailing membar if is_c1_or_interpreter_only(). Otherwise
> all volatile loads in C1 are preceded by a leading membar() so we don't
> need a trailing one as well.

Yes, OK. But the same applies to LIR_Assembler::casw() and casl().
Should I change those as well? I don't see any reason for them to be
different.

>
>>> 462 // By default, this operation has relaxed memory ordering
>
> No, it has whatever memory ordering you tell it. Plus, if you pass
> both acquire and release, sequential consistency.

If volatile load is implemented as "ldr ; dmb ishld" then this function
alone doesn't provide sequential consistency even with acquire and
release both set. That's why the original comment is misleading.

Can you suggest an alternate wording here? Perhaps we can delete all
mention of memory ordering and leave it up to the reader.

--
Thanks,
Nick