RFR: 8292868: Explicitly pass a third temp register to MacroAssembler::store_heap_oop for aarch64

Thu Aug 25 10:21:05 UTC 2022

Currently G1 (and Shenandoah) implicitly uses r3 on aarch64 in store_at.

This out of the blue register fixed for x86 in [JDK-8283186](https://bugs.openjdk.org/browse/JDK-8283186). This would be fixed in the same way on aarch64 by passing the temporary register explicitly so it is part of the GC api

Testing: Oracle aarch64 platforms tier 1-3

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Commit messages:
 - Remove implicit tmp register aarch64 store_at

Changes: https://git.openjdk.org/jdk/pull/10019/files
 Webrev: https://webrevs.openjdk.org/?repo=jdk&pr=10019&range=00
  Issue: https://bugs.openjdk.org/browse/JDK-8292868
  Stats: 68 lines in 16 files changed: 2 ins; 0 del; 66 mod
  Patch: https://git.openjdk.org/jdk/pull/10019.diff
  Fetch: git fetch https://git.openjdk.org/jdk pull/10019/head:pull/10019

PR: https://git.openjdk.org/jdk/pull/10019