RFR: 8292868: Explicitly pass a third temp register to MacroAssembler::store_heap_oop for aarch64

[Aleksey Shipilev]

On Thu, 25 Aug 2022 10:11:30 GMT, Axel Boldt-Christmas <aboldtch at openjdk.org> wrote:

> Currently G1 (and Shenandoah) implicitly uses r3 on aarch64 in store_at.
> 
> This out of the blue register fixed for x86 in [JDK-8283186](https://bugs.openjdk.org/browse/JDK-8283186). This would be fixed in the same way on aarch64 by passing the temporary register explicitly so it is part of the GC api
> 
> Testing: Oracle aarch64 platforms tier 1-3

Looks fine. I tested cross-builds on many platforms.

-------------

Marked as reviewed by shade (Reviewer).

PR: https://git.openjdk.org/jdk/pull/10019