Integrated: 8292868: Explicitly pass a third temp register to MacroAssembler::store_heap_oop for aarch64

[Axel Boldt-Christmas]

On Thu, 25 Aug 2022 10:11:30 GMT, Axel Boldt-Christmas <aboldtch at openjdk.org> wrote:

> Currently G1 (and Shenandoah) implicitly uses r3 on aarch64 in store_at.
> 
> This out of the blue register fixed for x86 in [JDK-8283186](https://bugs.openjdk.org/browse/JDK-8283186). This would be fixed in the same way on aarch64 by passing the temporary register explicitly so it is part of the GC api
> 
> Testing: Oracle aarch64 platforms tier 1-3

This pull request has now been integrated.

Changeset: f91943c1
Author:    Axel Boldt-Christmas <aboldtch at openjdk.org>
Committer: Erik Österlund <eosterlund at openjdk.org>
URL:       https://git.openjdk.org/jdk/commit/f91943c19fc0b060684a437d2c768461d54c088e
Stats:     68 lines in 16 files changed: 2 ins; 0 del; 66 mod

8292868: Explicitly pass a third temp register to MacroAssembler::store_heap_oop for aarch64

Reviewed-by: shade, eosterlund, tschatzl

-------------

PR: https://git.openjdk.org/jdk/pull/10019