RFR: 8293351: Add second tmp register to aarch64 BarrierSetAssembler::load_at [v2]

[Stuart Monteith]

On Tue, 6 Sep 2022 07:26:39 GMT, Axel Boldt-Christmas <aboldtch at openjdk.org> wrote:

>> I think the reason is that register r11 was used as temp register (and thus gets clobbered) by resolve_weak_handle previously. That's why this register was saved/restored here. But this has changed since it not used here anymore with your change. I am OK if you want to handle that in another PR. Just reminds. Thanks.
>
> I looked into it some further. You are correct. The reason I thought it was important was because this change hard crashed.
> 
> + __ str(r10, Address(__ pre(sp, -wordSize)));
> - __ stp(r10, r11, Address(__ pre(sp, -2 * wordSize)));
> 
> But I guess it is because I am misaligning the stack or there is some other reason `sp` cannot be bumped by `8`, only `16`. As this change is fine.
> 
> + __ str(r10, Address(__ pre(sp, -2 * wordSize)));
> - __ stp(r10, r11, Address(__ pre(sp, -2 * wordSize)));
> 
> Maybe using the RegSets and `push` would do this correctly, or it is some special invariant for these adapters.

The stackpointer needs 128 bit/64 byte alignment. use RegSets and` MacroAssembler::push(RegSet, sp);`, which will only push pairs of register. In this case: ` stp(r10, zr, Address(__ pre(sp, -2 * wordSize)));`

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PR: https://git.openjdk.org/jdk/pull/10161