RFR: 8293351: Add second tmp register to aarch64 BarrierSetAssembler::load_at [v2]

[Axel Boldt-Christmas]

On Tue, 6 Sep 2022 06:52:53 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Maybe? Actually looking at it a second time it seems like r0-r7 and r9-r17 are pushed to the stack at the vm call I was looking at. 
>> I am probably missing something. I do not fully understand the reason for pushing the registers at this point, not earlier or later. Would have to investigate further. I do however think that such a change belongs to a separate issue/PR. This PR should not change the instruction emission, only which registers are used.
>
> I think the reason is that register r11 was used as temp register (and thus gets clobbered) by resolve_weak_handle previously. That's why this register was saved/restored here. But this has changed since it not used here anymore with your change. I am OK if you want to handle that in another PR. Just reminds. Thanks.

I looked into it some further. You are correct. The reason I thought it was important was because this change hard crashed.

+ __ str(r10, Address(__ pre(sp, -wordSize)));
- __ stp(r10, r11, Address(__ pre(sp, -2 * wordSize)));

But I guess it is because I am misaligning the stack or there is some other reason `sp` cannot be bumped by `8`, only `16`. As this change is fine.

+ __ str(r10, Address(__ pre(sp, -2 * wordSize)));
- __ stp(r10, r11, Address(__ pre(sp, -2 * wordSize)));

Maybe using the RegSets and `push` would do this correctly, or it is some special invariant for these adapters.

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PR: https://git.openjdk.org/jdk/pull/10161