RFR: 8293769: RISC-V: Add a second temporary register for BarrierSetAssembler::load_at

[Fei Yang]

On Wed, 14 Sep 2022 03:40:30 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> This is similar to https://bugs.openjdk.org/browse/JDK-8293351
>> Add a second temporary register for BarrierSetAssembler::load_at GC API on riscv64.
>> Today G1 and Shenandoah uses a second temporary register. This will also be the case for generational ZGC.
>> 
>> Testing: Tier1-3 tested on Linux-riscv64 SiFive Unmatched board.
>
> Looks good to me. Thanks for the cleanup.

@feilongjiang @shipilev : Thanks for reviewing this. Integrate then.

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PR: https://git.openjdk.org/jdk/pull/10261