RFR: 8320807: [PPC64][ZGC] C1 generates wrong code for atomics

[Richard Reingruber]

On Mon, 27 Nov 2023 21:52:53 GMT, Martin Doerr <mdoerr at openjdk.org> wrote:

> Debugging test failures on PPC64 in java/lang/Thread/virtual/stress/Skynet.java#ZGenerational has shown that the ldarx+stdcx_ loop for uncompressed Oops in `LIR_Assembler::atomic_op` is wrong: `__ mr(Rtmp, Robj);` is inside of the ldarx+stdcx_ loop, but must be outside of it. Repeated execution leads to wrong store value.
> In addition, zBarrierSetC1.cpp expects `cas_obj` and `xchg` to contain all necessary memory barriers. That doesn't fit to the current PPC64 design which inserts memory barriers on LIR level instead. I've changed this and moved them into the assembler code for all GCs.
> While debugging, I have optimized out an unnecessary branch in `ZBarrierSetAssembler::store_barrier_medium`.

Looks good. Just two suggestions to improve comments.
Cheers, Richard.

src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp line 2603:

> 2601:   }
> 2602: 
> 2603:   // Volatile load may be followed by Unsafe CAS.

Suggestion:

  // There might be a volatile load before this Unsafe CAS.

src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp line 2984:

> 2982:   }
> 2983: 
> 2984:   // Volatile load may be followed by Unsafe OP.

Suggestion:

  // There might be a volatile load before this Unsafe OP.

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Marked as reviewed by rrich (Reviewer).

PR Review: https://git.openjdk.org/jdk/pull/16835#pullrequestreview-1759593616
PR Review Comment: https://git.openjdk.org/jdk/pull/16835#discussion_r1411967401
PR Review Comment: https://git.openjdk.org/jdk/pull/16835#discussion_r1411988559