RFR: 8338881: GenShen: Use explicit third temp register for post barrier

[Aleksey Shipilev]

On Fri, 23 Aug 2024 17:06:56 GMT, William Kemper <wkemper at openjdk.org> wrote:

> * Use register given as `tmp3` argument instead of "out of the blue" `r3`
> * Simplify logic for post barrier call
> 
> ## Testing
> GHA, internal pipelines

OK, so comprehension check. The deleted "Barrier needs uncompressed oop for region cross check." thing is copied from G1, which needed "original" value oop for the post-barrier to work. The call to `BSA::store_at` would compress `val`, destroying it. This is irrelevant for Shenandoah code, because we only pass the "location" for card table update, not the actual "value" we store. So this "corruption" is irrelevant. Saves some moves then, nice.

src/hotspot/cpu/aarch64/gc/shenandoah/shenandoahBarrierSetAssembler_aarch64.cpp line 422:

> 420: 
> 421:   bool in_heap = (decorators & IN_HEAP) != 0;
> 422:   bool needs_post_barrier = val != noreg && in_heap && ShenandoahCardBarrier;

Consider `(val != noreg)`.

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Marked as reviewed by shade (Committer).

PR Review: https://git.openjdk.org/shenandoah/pull/486#pullrequestreview-2257732779
PR Review Comment: https://git.openjdk.org/shenandoah/pull/486#discussion_r1729290600