RFR: 8322630: Remove ICStubs and related safepoints [v6]

[Robbin Ehn]

On Fri, 9 Feb 2024 09:53:29 GMT, Erik Österlund <eosterlund at openjdk.org> wrote:

>> src/hotspot/cpu/aarch64/aarch64.ad line 2224:
>> 
>>> 2222:   // This is the unverified entry point.
>>> 2223:   C2_MacroAssembler _masm(&cbuf);
>>> 2224:   __ ic_check(CodeEntryAlignment);
>> 
>> I'm not sure we want to increase the alignement to CodeEntryAlignment here.  I believe C2 already aligns the root block to CodeEntryAlignment.  @theRealAph, what do you think?
>
> I can change it to InteriorEntryAlignment which is what the VEP block is aligned to. I think it's still good that the root block is aligned to CodeEntryAlignment though. I heard some HW sheds some tears when their instruction cache lines also contain data that doesn't correspond to any actual instructions. But we can definitely align to InteriorEntryAlignment here.

To add to what Erik is saying here, we have notice that some CPU's have L1I and L1D exclusive, a cache-line can just be in of them. So you can end up with it bouncing between them.

Secondly, if an I-fetch gets data not intended to be decoded, the cpu can get upset in some cases.

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PR Review Comment: https://git.openjdk.org/jdk/pull/17495#discussion_r1484319136