[lworld+fp16] RFR: 8308363: Initial compiler support for FP16 scalar operations. [v4]

[Jatin Bhateja]

> Starting with 4th Generation Xeon, Intel has made extensive extensions to existing ISA to support 16 bit scalar and vector floating point operations based on IEEE 754 FP16 format.
> 
> We plan to support this in multiple stages spanning across Java side definition of Float16 type, scalar operation and finally SLP vectorization support.
> 
> This patch adds  minimal Java and Compiler side support for one API Float16.add.
> 
> Following is the gist of changes introduced with the patch :-
> 
> - Minimal implementation of Float16 primitive class supporting one operation (Float16.add)
> - X86 AVX512-FP16 feature detection at VM startup.
> - C2 IR and Inline expander changes for Float16.add API.
> - FP16 constant folding handling.
> - Backend support : Instruction selection patterns and assembler support.
> 
> Please review and share your feedback.
> 
> Best Regards,
> Jatin

Jatin Bhateja has updated the pull request incrementally with one additional commit since the last revision:

  Addressing offline review comments from Sandhya, new IR test addition.

-------------

Changes:
  - all: https://git.openjdk.org/valhalla/pull/848/files
  - new: https://git.openjdk.org/valhalla/pull/848/files/5cd42f3b..6989b465

Webrevs:
 - full: https://webrevs.openjdk.org/?repo=valhalla&pr=848&range=03
 - incr: https://webrevs.openjdk.org/?repo=valhalla&pr=848&range=02-03

  Stats: 247 lines in 11 files changed: 245 ins; 0 del; 2 mod
  Patch: https://git.openjdk.org/valhalla/pull/848.diff
  Fetch: git fetch https://git.openjdk.org/valhalla.git pull/848/head:pull/848

PR: https://git.openjdk.org/valhalla/pull/848