[lworld+fp16] RFR: 8308363: Initial compiler support for FP16 scalar operations.

[Jatin Bhateja]

Starting with 4th Generation Xeon, Intel has made extensive extensions to existing ISA to support 16 bit scalar and vector floating point operations based on IEEE 754 FP16 format.

We plan to support this in multiple stages spanning across Java side definition of Float16 type, scalar operation and finally SLP vectorization support.

This patch adds  minimal Java and Compiler side support for one API Float16.add.

Following is the gist of changes introduced with the patch :-

- Minimal implementation of Float16 primitive class supporting one operation (Float16.add)
- X86 AVX512-FP16 feature detection at VM startup.
- C2 IR and Inline expander changes for Float16.add API.
- FP16 constant folding handling.
- Backend support : Instruction selection patterns and assembler support.

Please review and share your feedback.

Best Regards,
Jatin

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Commit messages:
 - 8308363: Initial compiler support for FP16 scalar operations.

Changes: https://git.openjdk.org/valhalla/pull/848/files
 Webrev: https://webrevs.openjdk.org/?repo=valhalla&pr=848&range=00
  Issue: https://bugs.openjdk.org/browse/JDK-8308363
  Stats: 1413 lines in 22 files changed: 1404 ins; 3 del; 6 mod
  Patch: https://git.openjdk.org/valhalla/pull/848.diff
  Fetch: git fetch https://git.openjdk.org/valhalla.git pull/848/head:pull/848

PR: https://git.openjdk.org/valhalla/pull/848