Request for review (L): 6797305: Add LoadUB and LoadUI opcode class

[John Rose]

The sparc design for Address differs from x86 because there is no way  
to put a full-word displacement in, so there has to be provision for  
sethi, either automagically in a macro, or separately managed.  The  
relocation provides consistency between the sethi and the simm13  
field.  The two disp fields provide support for (a) the sethi/simm13  
usage, and (b) the actual simm13 field itself.  The sparc Address is  
two things, a syntax for rs1+simm13, and (more usefully) a way for  
managing part of what Intel calls addresses (but not scaling and  
double register modes).

With x64 we have a situation similar to sparc, since full 64-bit words  
don't fit into the addressing modes.  (Except for the special case of  
lea, which requires a temp, much like sparc.  See rscratch1 all over  
assembler_x86.cpp.)  Steve G. split out AddressLiteral as a way of  
expressing a possible multi-instruction addressing mode.

My new RegisterConstant stuff provides a way to build up address  
expressions by parts, emitting code only when necessary.  The risc  
way, of course, is to build addressing modes with multiple  
instructions as necessary, while the Intel way is to have a powerful  
set of HW-supported addressing modes, which we express by Address.   
This frays a little around the edges when we get to x64.

Maybe SPARC needs to change Address to rs1+{rs2,simm13} (i.e.,  
Register, RegisterConstant) and have a new AddressLiteral subtype that  
manages the multi-instruction use cases.

Not sure how to rationalize all this into correspondence, except by  
improving bit by bit as improvements occur to us.

-- John

On Mar 10, 2009, at 10:46 AM, Christian Thalinger wrote:

> Right, and I didn't know if that is the same as on x86, is it?  I  
> was a
> bit confused because of the relocate() call.