Request for review (L): 6797305: Add LoadUB and LoadUI opcode class

[Christian Thalinger]

On Tue, 2009-03-10 at 11:40 -0700, John Rose wrote:
> My new RegisterConstant stuff provides a way to build up address  
> expressions by parts, emitting code only when necessary.  The risc  
> way, of course, is to build addressing modes with multiple  
> instructions as necessary, while the Intel way is to have a powerful  
> set of HW-supported addressing modes, which we express by Address.   
> This frays a little around the edges when we get to x64.
> 
> Maybe SPARC needs to change Address to rs1+{rs2,simm13} (i.e.,  
> Register, RegisterConstant) and have a new AddressLiteral subtype that  
> manages the multi-instruction use cases.
> 
> Not sure how to rationalize all this into correspondence, except by  
> improving bit by bit as improvements occur to us.

Maybe I missing something here, but would it be possible to have a:

  Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) {

function on SPARC too, so it's possible to use $mem$$Address in the AD
file and let (Address src, Register dst)-signature functions decide
which emit function to call?  Furthermore we could assert on reg-reg
forms that have a displacement set, which is obviously wrong.

The only problem I see when using MacroAssembler instructions in
sparc.ad is the VerifyOops check in emit_form3_mem_reg.  Is that still
used/necessary or can it be moved somewhere else?

-- Christian