RFR: 8321215: Incorrect x86 instruction encoding for VSIB addressing mode

[Aleksey Shipilev]

On Mon, 4 Dec 2023 19:09:33 GMT, Sandhya Viswanathan <sviswanathan at openjdk.org> wrote:

> For instructions that use VSIB addressing mode (gather/scatter), the assembler incorrectly sets EVEX.X bit when the VSIB vector register is in the range XMM16 - XMM23. The EVEX.X bit should only be set when bit 3 of the register encoding is 1,  i.e. if the register encoding is 8 - 15 or 24 - 31.

I am curious which part of SDM it follows from?

In Intel SDM Vol 2, "2.6.1 Instruction Format and EVEX", I see:

"Operand specifier modifier bit for vector register: ... P[6] (Aleksey: EVEX.X) can also provide access to a high 16 vector register when SIB or VSIB addressing are not needed."

This "high 16" seems to differ from "upper 16" like you described, right? I.e. "high 16" means the 3-th bit set (XMM8...XMM15 or XMM24...XMM31), whereas "upper 16" means the actual "upper index" registers e.g. XMM16...XMM31)?

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PR Review: https://git.openjdk.org/jdk/pull/16957#pullrequestreview-1763275276