RFR: 8370473: C2: Better Aligment of Vector Spill Slots [v2]

[Richard Reingruber]

On Mon, 17 Nov 2025 03:25:33 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Richard Reingruber has updated the pull request incrementally with two additional commits since the last revision:
>> 
>>  - Enhance comment
>>  - Fix OptoAssembly for Power 8
>
> test/hotspot/jtreg/compiler/vectorapi/TestVectorSpilling.java line 79:
> 
>> 77:     @Test
>> 78:     @IR(counts = {IRNode.MEM_TO_REG_SPILL_COPY_TYPE, "vectorx", "> 0"},
>> 79:         phase = {CompilePhase.FINAL_CODE})
> 
> Hi, I find this IR test is failing on riscv where we are spilling a `vectora`. Maybe we should exclude this case?
> 
> 
> diff --git a/test/hotspot/jtreg/compiler/vectorapi/TestVectorSpilling.java b/test/hotspot/jtreg/compiler/vectorapi/TestVectorSpilling.java
> index 5e8b9341d8e..9d9a85e174c 100644
> --- a/test/hotspot/jtreg/compiler/vectorapi/TestVectorSpilling.java
> +++ b/test/hotspot/jtreg/compiler/vectorapi/TestVectorSpilling.java
> @@ -76,7 +76,8 @@ static void test16ByteSpilling_runner() {
> 
>      @Test
>      @IR(counts = {IRNode.MEM_TO_REG_SPILL_COPY_TYPE, "vectorx", "> 0"},
> -        phase = {CompilePhase.FINAL_CODE})
> +        phase = {CompilePhase.FINAL_CODE},
> +        applyIfCPUFeature= {"rvv", "false"})
>      static long test16ByteSpilling(long l1, long l2, long l3, long l4, long l5, long l6, long l7, long l8,
>                                     long l9 /* odd stack arg */) {
>          // To be scalar replaced and spilled to stack

Thanks @RealFYang for doing the testing. I've made the change you suggested.

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PR Review Comment: https://git.openjdk.org/jdk/pull/27969#discussion_r2534593378