RFR: 8301996: Move field resolution information out of the cpCache [v10]

[Dingli Zhang]

On Sat, 22 Jul 2023 13:04:23 GMT, Martin Doerr <mdoerr at openjdk.org> wrote:

>> Matias Saavedra Silva has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Missing semicolon
>
> src/hotspot/cpu/riscv/templateTable_riscv.cpp line 180:
> 
>> 178:       }
>> 179:       // Load-acquire the bytecode to match store-release in ResolvedFieldEntry::fill_in()
>> 180:       __ membar(MacroAssembler::AnyAny);
> 
> Why do you need this membar?

I am referencing the mapping from ARM memory operations onto RISC-V memory instructions in riscv-spec [1]:

> Since RISC-V does not currently have plain load and store opcodes with aq or rl annotations, ARM load-acquire and store-release operations should be mapped using fences instead. Furthermore, in order to enforce store-release-to-load-acquire ordering, there must be a FENCE RW,RW between the store-release and load-acquire;

So I am trying to be conservative here and added this membar to enforce store-release-to-load-acquire ordering. I can remove that if we are sure this is not necessary here.

[1] https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-1239329-2023-05-23/src/mm-eplan.adoc#armmappings

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PR Review Comment: https://git.openjdk.org/jdk/pull/14129#discussion_r1271653513