RFR: 8320069: RISC-V: Add Zcb instructions [v3]

[Robbin Ehn]

On Fri, 5 Jan 2024 09:15:52 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/assembler_riscv.hpp line 542:
>> 
>>> 540:   INSN(_lbu, 0b0000011, 0b100); // Zcb
>>> 541:   INSN(_lh,  0b0000011, 0b001); // Zcb
>>> 542:   INSN(_lhu, 0b0000011, 0b101); // Zcb
>> 
>> The code comment for these three lines seems a bit misleading. These are normal 4-bytes encoding load/store instructions, not `Zcb` compressed instructions.
>
> The comment was suppose to mean, these are 'overridden' by zcb, not C as the others.
> I'll clarify that.

I remove them, fixed.

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PR Review Comment: https://git.openjdk.org/jdk/pull/17122#discussion_r1442683028