RFR: 8334999: RISC-V: implement AES single block encryption/decryption intrinsics [v2]

[Fei Yang]

On Sun, 7 Jul 2024 15:16:02 GMT, ArsenyBochkarev <duke at openjdk.org> wrote:

>> Hello everyone! Please review this port of vector AES single block encryption/decryption intrinsics. On my QEMU with `Zvkned` extension enabled the `test/hotspot/jtreg/compiler/codegen/aes/TestAESMain.java` test is OK. I know that currently hardware implementing this extension is not available on the market but I suppose this PR can be a good starting point on supporting AES intrinsics for RISC-V in OpenJDK.
>
> ArsenyBochkarev has updated the pull request incrementally with three additional commits since the last revision:
> 
>  - Use t2 directly instead of temp2
>  - Rename temp1 -> x0
>  - Left a note on a side effect of generate_vle32_pack4

src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 2282:

> 2280:     __ vrev8_v(vtmp1, vtmp1);
> 2281:     __ vrev8_v(vtmp2, vtmp2);
> 2282:   }

Please leave a new line after each of these newly-added functions.

src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 2332:

> 2330:     const Register key         = c_rarg2;  // key array address
> 2331:     const Register keylen      = c_rarg3;
> 2332:     const Register x0          = c_rarg4;

I think you can use the global `x0` (aka the zero register) instead for `vsetivli`. It very confusing to have register alias names like `x0` like here.

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PR Review Comment: https://git.openjdk.org/jdk/pull/19960#discussion_r1668794931
PR Review Comment: https://git.openjdk.org/jdk/pull/19960#discussion_r1668790141