RFR: 8334999: RISC-V: implement AES single block encryption/decryption intrinsics [v2]

[Fei Yang]

On Mon, 8 Jul 2024 14:53:03 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> ArsenyBochkarev has updated the pull request incrementally with three additional commits since the last revision:
>> 
>>  - Use t2 directly instead of temp2
>>  - Rename temp1 -> x0
>>  - Left a note on a side effect of generate_vle32_pack4
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 2282:
> 
>> 2280:     __ vrev8_v(vtmp1, vtmp1);
>> 2281:     __ vrev8_v(vtmp2, vtmp2);
>> 2282:   }
> 
> Please leave a new line after each of these newly-added functions.

BTW: Did you compare this with the openssl version which also makes use of `vaesz_vs` instruction from `Zvkned`  [1]? 

[1] https://github.com/openssl/openssl/blob/master/crypto/aes/asm/aes-riscv64-zvkb-zvkned.pl

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PR Review Comment: https://git.openjdk.org/jdk/pull/19960#discussion_r1670009486