RFR: 8345298: RISC-V: Add riscv backend for Float16 operations - scalar [v5]

[Fei Yang]

On Mon, 10 Mar 2025 17:23:15 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/vm_version_riscv.hpp line 301:
>> 
>>> 299:   static bool supports_fencei_barrier() { return ext_Zifencei.enabled(); }
>>> 300: 
>>> 301:   static bool supports_float16_float_conversion() {
>> 
>> Is it safe to simply rename this as `supports_float16` like other CPUs? I suppose it will still work in functionality even if we only have the `Zfhmin` extension, right?
>
> In fact, I think `supports_float16` is confusing, in particular on riscv, as e.g. `AddHF` requires `UseZfh`, but `ConvF2HF` requires `UseZfh || UseZfhmin`, so I think it's better to keep supports_float16_float_conversion, as its naming is much more explicit and clearer.

OK!

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PR Review Comment: https://git.openjdk.org/jdk/pull/23844#discussion_r1988207520