Seeing error in one test on ARM: org.openjdk.jcstress.tests.volatiles.ReadTwiceOverVolatileReadTest

[White, Derek]

OK, Thanks Aleksey!

Here's a follow-up question for anyone that wants to play along:

The related ARM restrictions are:
 "
* Reads and writes to the same address are coherent within the shareability domain of the memory address
being accessed.

* Two reads to the same address by the same observer are observed in program order by all observers within
the shareability domain of the memory address being accessed.
"

I think this means that this statement is true for ARM (although not JMM):
- Given that one (and only one) core is incrementing a memory location, with or without memory barriers or atomic instructions,
- Another core reading that same memory location (with or without memory barriers, etc), will never see writes out of order. 
	- It may never see ANY writes, absent memory barriers, etc.
	- It might never see various intermediate values. 
	- But a read later in program order should not see a value lower than a read earlier in program order.
- And the preceding is true for multiple cores reading that same memory location.
	- Noting that there are no restrictions between the reads from different cores, only the reads within each core.
- And by "core" I mean "observer", "processing element", or abstraction of your choice.

Does this seem correct?

You might be able to foresee a test case in the future...

 - Derek

-----Original Message-----
From: Aleksey Shipilev [mailto:shade at redhat.com] 
Sent: Thursday, February 23, 2017 2:36 PM
To: White, Derek <Derek.White at cavium.com>; jcstress-dev at openjdk.java.net
Subject: Re: Seeing error in one test on ARM: org.openjdk.jcstress.tests.volatiles.ReadTwiceOverVolatileReadTest

On 02/23/2017 07:52 PM, White, Derek wrote:
> 1) One explanation for this is that the load of w12 completed 
> out-of-order before the load of w10, so it saw the initial order. But 
> this seems to violate the requirement that: " Two reads to the same 
> address by the same observer are observed in program order by all 
> observers within the shareability domain of the memory address being 
> accessed." B2.7.2, ARM ARM v8. This requirement is independent of the LDAR of w11.

Yes, that's "coherence": a single modification order for a particular location.

> 2) The LDAR adds the additional requirement (paraphrased by cancelling 
> out text of shareability domains): "For a Load-Acquire, observers 
> observe accesses in the following order: 1. The read caused by the Load-Acquire. 2.
> Reads and writes caused by loads and stores that appear in program 
> order after the Load-Acquire requires that the observer observes the access."
> B2.7.3.

> There is so much verbiage in the original text, but this seems to 
> imply that the load into w12 can't move above the ldar of w11. But 
> this restriction by itself doesn't prevent an earlier load being 
> delayed after the ldar. So if the 1st and 3rd  loads had different 
> source virtual addresses then the load of w10 could have been delayed after the load of w12.

Yes. Where coherence comes into play again.

Thanks,
-Aleksey