[riscv-port] Integrated: 8278033: riscv: Fix MacroAssembler::atomic_incw: store condition instruction has wrong operand order

[Xiaolin Zheng]

On Wed, 1 Dec 2021 02:40:31 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

> This is a trivial fix for this typo. This could reproduce before JDK18 by using `-XX:+PrintBiasedLockingStatistics`; however, after the removal of BiasedLocking, this function has no usage now. But we might fix it as well for future usage since it is a quite fundamental function. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/11)

This pull request has now been integrated.

Changeset: 8239cbb3
Author:    Xiaolin Zheng <xlinzheng at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/8239cbb38e3ea0e1b4c840294ad9578ef687d2d5
Stats:     1 line in 1 file changed: 0 ins; 0 del; 1 mod

8278033: riscv: Fix MacroAssembler::atomic_incw: store condition instruction has wrong operand order

Reviewed-by: fyang

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PR: https://git.openjdk.java.net/riscv-port/pull/19