[riscv-port] RFR: 8278833: riscv: Remove the x3 and x4 register saving logic in register savers [v2]

[Xiaolin Zheng]

On Wed, 15 Dec 2021 08:57:45 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp line 198:
>> 
>>> 196:   for (int i = 5; i < RegisterImpl::number_of_registers; i++, sp_offset_in_slots += step_in_slots) {
>>> 197:     Register r = as_Register(i);
>>> 198:     if (r != xthread && r != t0 && r != t1) {
>> 
>> Why not start the loop from x7?
>
> Thanks for the nice reminder -- changed.

Need some testing work for the new change -- I will ping this thread after tests are done.

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PR: https://git.openjdk.java.net/riscv-port/pull/31