[riscv-port] RFR: 8277036: riscv: Get CPU features from the auxiliary vector on Linux [v2]

[Fei Yang]

On Fri, 19 Nov 2021 04:01:46 GMT, Yanhong Zhu <yzhu at openjdk.org> wrote:

>> Due to the lack of native environment in our early development of riscv port, we detect riscv CPU ISA extensions through checking whether simulator (e.g. QEMU) supports execution of one of the instructions in the corresponding feature spec or not. Fortunately, there are several riscv hardwares available now, we can directly get this CPU info from the auxiliary vector on Linux. Note that the aarch64 port also did the same thing on Linux platform. This also fixes some whitespace issue reported by jcheck.
>> 
>> This has been tested on HiFive Unleashed board (rv64imafdc) and NeZha D1 board (rv64imafdcvu):
>> 
>> # HiFive Unmatched
>> $jdk/bin/java -XX:+UseVExt -XX:+PrintFlagsFinal -version |grep UseVExt
>> OpenJDK 64-Bit Server VM warning: RVV is not supported on this CPU
>>     bool UseVExt                                          = false                             {ARCH product} {command line}
>> openjdk version "18-internal" 2022-03-15
>> OpenJDK Runtime Environment (build 18-internal+0-adhoc..riscv-port)
>> OpenJDK 64-Bit Server VM (build 18-internal+0-adhoc..riscv-port, mixed mode)
>> 
>> $jdk/bin/java -XX:-UseVExt -XX:+PrintFlagsFinal -version |grep UseVExt
>>     bool UseVExt                                          = false                             {ARCH product} {command line}
>> openjdk version "18-internal" 2022-03-15
>> OpenJDK Runtime Environment (build 18-internal+0-adhoc..riscv-port)
>> OpenJDK 64-Bit Server VM (build 18-internal+0-adhoc..riscv-port, mixed mode)
>> 
>> $jdk/bin/java -XX:+PrintFlagsFinal -version |grep UseVExt
>>     bool UseVExt                                          = false                             {ARCH product} {command line}
>> openjdk version "18-internal" 2022-03-15
>> OpenJDK Runtime Environment (build 18-internal+0-adhoc..riscv-port)
>> OpenJDK 64-Bit Server VM (build 18-internal+0-adhoc..riscv-port, mixed mode)
>> 
>> # NeZha D1 
>> $jdk/bin/java -XX:+UseVExt -XX:+PrintFlagsFinal -version |grep UseVExt
>>     bool UseVExt                                          = true                             {ARCH product} {command line}
>> openjdk version "18-internal" 2022-03-15
>> OpenJDK Runtime Environment (build 18-internal+0-adhoc..riscv-port)
>> OpenJDK 64-Bit Server VM (build 18-internal+0-adhoc..riscv-port, mixed mode)
>> 
>> $jdk/bin/java -XX:-UseVExt -XX:+PrintFlagsFinal -version |grep UseVExt
>>     bool UseVExt                                          = false                             {ARCH product} {command line}
>> openjdk version "18-internal" 2022-03-15
>> OpenJDK Runtime Environment (build 18-internal+0-adhoc..riscv-port)
>> OpenJDK 64-Bit Server VM (build 18-internal+0-adhoc..riscv-port, mixed mode)
>> 
>> $jdk/bin/java -XX:+PrintFlagsFinal -version |grep UseVExt
>>     bool UseVExt                                          = false                             {ARCH product} {command line}
>> openjdk version "18-internal" 2022-03-15
>> OpenJDK Runtime Environment (build 18-internal+0-adhoc..riscv-port)
>> OpenJDK 64-Bit Server VM (build 18-internal+0-adhoc..riscv-port, mixed mode)
>
> Yanhong Zhu has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Add checking for B & C extension

Changes requested by fyang (Lead).

src/hotspot/cpu/riscv/vm_version_riscv.hpp line 44:

> 42: 
> 43:   enum Feature_Flag {
> 44: #define CPU_FEATURE_FLAGS(decl)               \

Please keep those macros in the same order as the HWCAP_ISA_X macros in file vm_version_linux_riscv.cpp.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/10