[riscv-port] RFR: 8277883: riscv: Fix a temp register usage in eden_allocate

[Fei Yang]

On Mon, 29 Nov 2021 03:43:32 GMT, zhengxiaolinX <duke at openjdk.java.net> wrote:

> Hi team,
> 
> A trivial fix for a small C1 crash - this issue could be directly reproduced by using `java -XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1`. The reason is simple: the eden_allocate uses t2 as a register and zaps it, whereas C1 will use it as a register allocation candidate, leading to a crash. In this function, t0 never gets a use so we can use it safely. Tested in all cases. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/15)
> 
> Thanks,
> Xiaolin

Changes requested by fyang (Lead).

src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.cpp line 182:

> 180:     __ bind(retry);
> 181: 
> 182:     Register tmp = t0;

No need to introduce local variable "tmp" here. I think we can use t0 directly here.

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PR: https://git.openjdk.java.net/riscv-port/pull/16