[riscv-port] RFR: 8277883: riscv: Fix a temp register usage in eden_allocate [v2]

zhengxiaolinX duke at openjdk.java.net
Mon Nov 29 08:14:00 UTC 2021

On Mon, 29 Nov 2021 07:46:53 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> zhengxiaolinX has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR. The pull request contains one new commit since the last revision:
>>   Fix a temp register usage in eden_allocate
> src/hotspot/cpu/riscv/gc/shared/barrierSetAssembler_riscv.cpp line 182:
>> 180:     __ bind(retry);
>> 181: 
>> 182:     Register tmp = t0;
> No need to introduce local variable "tmp" here. I think we can use t0 directly here.

This is a reasonable point -- changed as proposal, passed fastdebug build, and tested a simple `java -XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1`.


PR: https://git.openjdk.java.net/riscv-port/pull/16

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