[riscv-port] RFR: 8277883: riscv: Fix a temp register usage in eden_allocate [v2]

[zhengxiaolinX]

> Hi team,
> 
> A trivial fix for a small C1 crash - this issue could be directly reproduced by using `java -XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1`. The reason is simple: the eden_allocate uses t2 as a register and zaps it, whereas C1 will use it as a register allocation candidate, leading to a crash. In this function, t0 never gets a use so we can use it safely. Tested in all cases. [The original patch](https://github.com/riscv-collab/riscv-openjdk/pull/15)
> 
> Thanks,
> Xiaolin

zhengxiaolinX has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR. The pull request contains one new commit since the last revision:

  Fix a temp register usage in eden_allocate

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/16/files
  - new: https://git.openjdk.java.net/riscv-port/pull/16/files/b37dd6d3..ed811e74

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=16&range=01
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=16&range=00-01

  Stats: 6 lines in 1 file changed: 0 ins; 2 del; 4 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/16.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/16/head:pull/16

PR: https://git.openjdk.java.net/riscv-port/pull/16