[riscv-port] Integrated: 8277890: riscv: fix the infinite LR/SC loop in BarrierSetAssembler::eden_allocate

[Yadong Wang]

On Mon, 29 Nov 2021 15:06:51 GMT, Yadong Wang <yadongwang at openjdk.org> wrote:

> This bug can be reproduced by `java -XX:+UseSerialGC -XX:-UseTLAB -XX:TieredStopAtLevel=1 -version` on the unmatched board where this command will hang. The reason is that the implementation of load reserved/store conditional loop in BarrierSetAssembler::eden_allocate breaks the RISC-V Atomic extension spec:
> 
> For the
> sequence to be guaranteed to eventually succeed, the dynamic code executed between the LR and
> SC instructions can only contain other instructions from the base \I" subset, excluding loads, stores,
> backward jumps or taken backward branches, FENCE, FENCE.I, and SYSTEM instructions.
> 
> It may cause an unspecified behaviour depends on specific hardware implementations.

This pull request has now been integrated.

Changeset: 5bb7f8bb
Author:    Yadong Wang <yadongwang at openjdk.org>
Committer: Fei Yang <fyang at openjdk.org>
URL:       https://git.openjdk.java.net/riscv-port/commit/5bb7f8bb4feeed2b090ebd8038a06f5bfd7dec98
Stats:     24 lines in 1 file changed: 12 ins; 8 del; 4 mod

8277890: riscv: fix the infinite LR/SC loop in BarrierSetAssembler::eden_allocate

Reviewed-by: fyang

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PR: https://git.openjdk.java.net/riscv-port/pull/17