[riscv-port] RFR: 8277968: riscv: detect vector extension with vcsr

kuaiwei duke at openjdk.java.net
Tue Nov 30 07:27:33 UTC 2021

UseRVV could cause crash on D1 board(RISCV-C906).

It seems that though the D1 board is equipped with RVV-0.7.1[1] . In our test, VLENB CSR can return value of 16 on D1 board. So JDK will assume it can support RVV extension and crash in vector instructions when  UseRVV is enabled.  

RVV-0.9 and above[2] introduce a new VCSR CSR register, it will raise SIGILL on D1 board. So we can check it to detect vext support.

[1] https://github.com/riscv/riscv-v-spec/blob/0a24d0f61b5cd3f1f9265e8c40ab211daa865ede/v-spec.adoc#vector-extension-programmers-model
[2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-extension-programmers-model


Commit messages:
 - 8277968: riscv: detect vector extension with vcsr

Changes: https://git.openjdk.java.net/riscv-port/pull/18/files
 Webrev: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=18&range=00
  Issue: https://bugs.openjdk.java.net/browse/JDK-8277968
  Stats: 88 lines in 4 files changed: 81 ins; 6 del; 1 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/18.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/18/head:pull/18

PR: https://git.openjdk.java.net/riscv-port/pull/18

More information about the riscv-port-dev mailing list