[riscv-port] RFR: 8277968: riscv: Detect vector extension with vcsr [v2]
duke at openjdk.java.net
Tue Nov 30 08:04:52 UTC 2021
> UseRVV could cause crash on D1 board(RISCV-C906).
> It seems that though the D1 board is equipped with RVV-0.7.1 . In our test, VLENB CSR can return value of 16 on D1 board. So JDK will assume it can support RVV extension and crash in vector instructions when UseRVV is enabled.
> RVV-0.9 and above introduce a new VCSR CSR register, it will raise SIGILL on D1 board. So we can check it to detect vext support.
>  https://github.com/riscv/riscv-v-spec/blob/0a24d0f61b5cd3f1f9265e8c40ab211daa865ede/v-spec.adoc#vector-extension-programmers-model
>  https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-extension-programmers-model
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8277968: riscv: Detect vector extension with vcsr
- all: https://git.openjdk.java.net/riscv-port/pull/18/files
- new: https://git.openjdk.java.net/riscv-port/pull/18/files/380bb30b..fecbfefd
- full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=18&range=01
- incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=18&range=00-01
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