[riscv-port] RFR: 8282331: riscv: is_wide_vector should not depend on specific vector size [v5]

[Feilong Jiang]

> RISC-V Vector Extension adds 32 architectural vector registers to the base scalar RISC-V ISA, and did not overlay the f registers on v registers. `is_wide_vector` should always return true when RVV is enabled. , `is_wide_vector` should always return true when RVV is enabled. 
> On AArch64, the thirty two registers in the FP/SIMD register bank named V0 to V31 are used to hold floating point  operands for the scalar floating point instructions, and both scalar and vector operands for the Advanced SIMD instructions. 8 bytes vectors registers are saved by default on AArch64.
> 
> Tier1 tests on QEMU with UseRVV enabled are passed without new failures.

Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:

  polish comments

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Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/59/files
  - new: https://git.openjdk.java.net/riscv-port/pull/59/files/3b53c1f2..70ac2ca3

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=59&range=04
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=59&range=03-04

  Stats: 2 lines in 1 file changed: 0 ins; 1 del; 1 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/59.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/59/head:pull/59

PR: https://git.openjdk.java.net/riscv-port/pull/59