[riscv-port] RFR: 8279346: riscv: Unnecessary sign extension in BigInteger intrinsics

[Fei Yang]

On Fri, 31 Dec 2021 09:13:47 GMT, Yanhong Zhu <yzhu at openjdk.org> wrote:

> Reference: https://github.com/riscv-non-isa/riscv-elf-psabi-doc
> 
> " Scalars that are at most XLEN bits wide are passed in a single argument register, or on the stack by value if none is available.
> When passed in registers or on the stack, integer scalars narrower than XLEN bits are widened according to the sign of their type up to 32 bits, then sign-extended to XLEN bits.
> When passed in registers or on the stack, floating-point types narrower than XLEN bits are widened to XLEN bits, with the upper bits undefined."
> 
> So there is no need to do sign extension for signed integer input parameters.
> 
> Performed full jtreg tests with qemu without new failures.

Looks good.

-------------

Marked as reviewed by fyang (Lead).

PR: https://git.openjdk.java.net/riscv-port/pull/40