[riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation instructions [v8]
Fei Yang
fyang at openjdk.java.net
Tue Jan 4 06:14:31 UTC 2022
On Tue, 4 Jan 2022 03:36:24 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:
>> This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw. New C2 instructions are covered by following JTREG tests:
>> - test/hotspot/jtreg/compiler/intrinsics/TestRotate.java
>> - test/jdk/java/lang
>>
>> This PR also add zext/bext C2 instructions that were missed in JDK-8279213
>>
>> Hotspot and jdk tier1 test on QEMU (enable RVB) are passed without new failures.
>
> Feilong Jiang has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR.
Changes requested by fyang (Lead).
src/hotspot/cpu/riscv/riscv_b.ad line 166:
> 164:
> 165: // unsigned int to short
> 166: instruct convUI2S_reg_reg_rvb(iRegINoSp dst, iRegIorL2I src, immI_16bits mask) %{
We should rename this from convUI2S_reg_reg_rvb to convS2UI_reg_reg_rvb. Please also update the comments.
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PR: https://git.openjdk.java.net/riscv-port/pull/39
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