[riscv-port] RFR: 8279344: riscv: RVB: Add bitwise rotation instructions [v8]

[Feilong Jiang]

> This PR implements bitwise instructions of RISC-V BitManipulation Extension, including ror/rolw/ror/rori/roriw/rorw. New C2 instructions are covered by following JTREG tests:
> - test/hotspot/jtreg/compiler/intrinsics/TestRotate.java
> - test/jdk/java/lang 
> 
> This PR also add zext/bext C2 instructions that were missed in JDK-8279213
> 
> Hotspot and jdk tier1 test on QEMU (enable RVB) are passed without new failures.

Feilong Jiang has refreshed the contents of this pull request, and previous commits have been removed. The incremental views will show differences compared to the previous content of the PR. The pull request contains one new commit since the last revision:

  update copyright to 2022

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Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/39/files
  - new: https://git.openjdk.java.net/riscv-port/pull/39/files/fe673075..1c519c74

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=07
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=39&range=06-07

  Stats: 2 lines in 1 file changed: 0 ins; 1 del; 1 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/39.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/39/head:pull/39

PR: https://git.openjdk.java.net/riscv-port/pull/39