[riscv-port] RFR: 8278994: riscv: RVC support [v10]

[Fei Yang]

On Mon, 10 Jan 2022 03:04:25 GMT, Xiaolin Zheng <xlinzheng at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/assembler_riscv.hpp line 2409:
>> 
>>> 2407:   }
>>> 2408: 
>>> 2409: #define IF(BOOL, ...)       IF_##BOOL(__VA_ARGS__)
>> 
>> maybe better to expand those macros directly?
>
> Unfortunately, this could not be easily done by substituting by a simple `assert_cond(!CHECK_RD || Rd != x0);` because of some details:
> `c_ldsp` and `c_fldsp` use `Register` and `FloatRegister` separately so there is a type-related problem: x0 is only one `Register` and only `c_ldsp` needs this sanity check. So these macros here are trying to make sure this check isn't generated by `c_fldsp` at all because checking `Rd(a float register) != x0` will result in compilation errors.

Yes, I know the issue you are trying to resolve. Actually, I prefer to have two INSN macro definitions here: one for the integer case and one for the floating point case. That will be cleaner.

-------------

PR: https://git.openjdk.java.net/riscv-port/pull/34