[riscv-port] RFR: 8278994: riscv: RVC support [v10]

[Xiaolin Zheng]

On Mon, 10 Jan 2022 03:17:48 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Unfortunately, this could not be easily done by substituting by a simple `assert_cond(!CHECK_RD || Rd != x0);` because of some details:
>> `c_ldsp` and `c_fldsp` use `Register` and `FloatRegister` separately so there is a type-related problem: x0 is only one `Register` and only `c_ldsp` needs this sanity check. So these macros here are trying to make sure this check isn't generated by `c_fldsp` at all because checking `Rd(a float register) != x0` will result in compilation errors.
>
> Yes, I know the issue you are trying to resolve. Actually, I prefer to have two INSN macro definitions here: one for the integer case and one for the floating point case. That will be cleaner.

done - thanks for the suggestions of splitting the two macros.

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PR: https://git.openjdk.java.net/riscv-port/pull/34