[riscv-port] RFR: 8279827: riscv: RVB: Add shift and add instructions [v3]

[Feilong Jiang]

> This PR implements shift left and add instructions: `sh1add`/`sh2add`/`sh3add`/`sh1add.uw`/`sh2add.uw`/`sh3add.uw`.
> 
> New C2 instructions are covered by JTREG test: test/jdk/java/lang

Feilong Jiang has updated the pull request incrementally with two additional commits since the last revision:

 - move uncommon shamt 0 to else branch
 - merge shxadd instructs into one instruct

-------------

Changes:
  - all: https://git.openjdk.java.net/riscv-port/pull/43/files
  - new: https://git.openjdk.java.net/riscv-port/pull/43/files/bb1b8580..f166a82b

Webrevs:
 - full: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=43&range=02
 - incr: https://webrevs.openjdk.java.net/?repo=riscv-port&pr=43&range=01-02

  Stats: 183 lines in 3 files changed: 10 ins; 150 del; 23 mod
  Patch: https://git.openjdk.java.net/riscv-port/pull/43.diff
  Fetch: git fetch https://git.openjdk.java.net/riscv-port pull/43/head:pull/43

PR: https://git.openjdk.java.net/riscv-port/pull/43