[riscv-port] RFR: 8279827: riscv: RVB: Add shift and add instructions [v2]

[Feilong Jiang]

On Wed, 12 Jan 2022 00:58:40 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Feilong Jiang has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   match iRegI instead of iRegIorL2I
>
> src/hotspot/cpu/riscv/riscv.ad line 3030:
> 
>> 3028:   interface(CONST_INTER);
>> 3029: %}
>> 3030: 
> 
> I think it will be better to introduce one new immIScale which combines all three.
> Then we can combine the newly-added instructs and reduce redundancy. If you do that, you will also need a new enc_class for distinguishing between the different Zba shift instruction encodings.
> 
> // Scale/Shift values for Zba instructions
> operand immIScale()
> %{
> predicate(0 <= n->get_int() && (n->get_int() <= 3));
> match(ConI);
> op_cost(0);
> format %{ %}
> interface(CONST_INTER);
> %}

Thank you for the suggestion. It's maybe better to call the `shadd` under macroAssembler (where t0 is actually not used) to avoid the reduction definition of enc_class. New commits pushed.

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PR: https://git.openjdk.java.net/riscv-port/pull/43